2 Meg x 16, 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
Features
Async/Page CellularRAM
TM
1.0 Memory
MT45W2MW16PA
MT45W1MW16PA*
*Note: Please contact the factory for all new 16Mb designs.
For the latest data sheet, refer to Micron’s Web site:
http://www.micron.com/products/psram/cellularram/
Features
• Asynchronous and page mode interface
• Random access time: 70ns, 85ns
• V
CC
, V
CC
Q voltages
1.70V–1.95V V
CC
1.70V–3.30V V
CC
Q
• Page mode read access
Sixteen-word page size
Interpage read access: 70ns, 85ns
Intrapage read access: 20ns, 25ns
• Low power consumption
Asynchronous READ: <20mA
Intrapage READ: <15mA
Standby: 110µA (32Mb – standard), 80µA (16Mb)
90µA (32Mb – low-power option)
Deep power-down: <10µA (TYP @ 25°C)
• Low-power features
Temperature compensated refresh (TCR)
On-chip temperature sensor
Partial array refresh (PAR)
Deep power-down (DPD) mode
Figure 1:
Ball Assignment – 48-Ball VFBGA
1
A
B
C
D
E
F
G
H
LB#
2
OE#
3
A0
4
A1
5
A2
6
ZZ#
DQ8
UB#
A3
A4
CE#
DQ0
DQ9
DQ10
A5
A6
DQ1
DQ2
V
SS
Q
DQ11
A17
A7
DQ3
V
CC
V
CC
Q
DQ12
NC
A16
DQ4
V
SS
DQ14
DQ13
A14
A15
DQ5
DQ6
DQ15
A19
A12
A13
WE#
DQ7
A18
A8
A9
A10
A11
A20
Options
• Configuration
2 Meg x 16
1 Meg x 16
• Package
48-ball VFBGA (standard)
48-ball VFBGA (lead-free)
• Access time
70ns
85ns
• Standby power
Standard
Low-power (32Mb)
Designator
MT45W2MW16PA
MT45W1MW16PA
1
FA
BA
1
-70
-85
None
L
Top View
(Ball Down)
Options (continued)
• Operating temperature range
Wireless (-30°C to +85°C)
Industrial (-40°C to +85°C)
Designator
WT
2
IT
3
Notes: 1.Please contact the factory for all new 16Mb
designs.
2. -30°C exceeds the CellularRAM Workgroup
1.0 specification of -25°C.
3. Contact factory.
Part Number Example:
MT45W2MW16PAFA-70LWT
PDF: 09005aef80d481d3/Source: 09005aef80d48266
Async CellularRAM_16_32__1.fm - Rev. E 10/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2 Meg x 16, 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
Table of Contents
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Configuration Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Access Using ZZ# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Partial Array Refresh (CR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Temperature Compensated Refresh (CR[6:5]) Default = On-Chip Temperature Sensor . . . . . . . . . . . . . . . . .15
Page Mode READ Operation (CR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PDF: 09005aef80d481d3/Source: 09005aef80d48266
Async CellularRAM_16_32TOC.fm - Rev. E 10/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
2 Meg x 16, 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Ball Assignment – 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagram 2 Meg x 16 and 1 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Page READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Software Access PAR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Load Configuration Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Software Access Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Software Access Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Configuration Register Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Typical Refresh Current vs. Temperature (I
TCR
) – 32Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Typical Refresh Current vs. Temperature (I
TCR
) – 16Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power-Up Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Deep Power-Down – Entry/Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Single READ Operation (WE# = V
IH
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Page Mode READ Operation (WE# = V
IH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WRITE Cycle (WE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE Cycle (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE Cycle (LB#/UB# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PDF: 09005aef80d481d3/Source: 09005aef80d48266
Async CellularRAM_16_32LOF.fm - Rev. E 10/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
2 Meg x 16, 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
32Mb Address Patterns for PAR (CR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
16Mb Address Patterns for PAR (CR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Maximum Standby Currents for Applying PAR and TCR Settings – 32Mb. . . . . . . . . . . . . . . . . . . . . . .19
Maximum Standby Currents for Applying PAR and TCR Settings – 32Mb Low-Power (L). . . . . . . . .19
Maximum Standby Currents for Applying PAR and TCR Settings – 16Mb. . . . . . . . . . . . . . . . . . . . . . .20
Deep Power-Down Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Capacitance Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Power-Up Initialization Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Deep Power-Down Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Page Mode READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PDF: 09005aef80d481d3/Source: 09005aef80d48266
Async CellularRAM_16_32LOT.fm - Rev. E 10/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
2 Meg x 16, 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
General Description
General Description
Micron
®
CellularRAM™ products are high-speed, CMOS PSRAM memories developed
for low-power, portable applications. The MT45W2MW16PA is a 32Mb DRAM core
device organized as 2 Meg x 16 bits, and the MT45W1MW16PA is a 16Mb DRAM core
device organized as 1 Meg x 16 bits. These devices include the industry-standard, asyn-
chronous memory interface found on other low-power SRAM or Pseudo SRAM offerings.
A user-accessible configuration register (CR) defines how the CellularRAM device per-
forms on-chip refresh and whether page mode read accesses are permitted. This register
is automatically loaded with a default setting during power-up and can be updated at
any time during normal operation.
To operate seamlessly on an asynchronous memory bus, CellularRAM products incor-
porate a transparent self refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
Special attention has been focused on current consumption during self refresh. Cellular-
RAM products include three system-accessible mechanisms to minimize refresh cur-
rent. Temperature compensated refresh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The refresh rate decreases at lower tem-
peratures to minimize current consumption during standby. TCR can also be set by the
system for maximum device temperatures of +85°C, +45°C, and +15°C. Setting sleep
enable (ZZ#) to LOW enables one of two low-power modes: partial array refresh (PAR) or
deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that
contains essential data. DPD halts refresh operation altogether and is used when no vital
information is stored in the device. These three refresh mechanisms are accessed
through the CR.
Figure 2:
Functional Block Diagram 2 Meg x 16 and 1 Meg x 16
A[20:0]
(for 32Mb)
A[19:0]
(for 16Mb)
Address Decode
Logic
2,048K x 16
(1,024K x 16)
DRAM
Memory
Array
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
Configuration
Register (CR)
CE#
WE#
OE#
UB#
LB#
ZZ#
Control
Logic
Note:
Functional block diagrams illustrate simplified device operation. See truth table, ball
descriptions, and timing diagrams for detailed information.
PDF: 09005aef80d481d3/Source: 09005aef80d48266
Async CellularRAM_16_32__2.fm - Rev. E 10/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
